1. Field of the invention
The present invention relates to an integrated circuit (IC) having a controlled on-chip impedance.
2. Description of the Prior Art
Most integrated circuit (IC) on-chip impedance circuits exhibit a large variation in value with variation in process, temperature and power supply voltage (e.g., V.sub.dd) if they are passive, or with variation in common mode voltage if they are active. Many high speed signaling circuits use a low termination impedance (typically .about.50 ohms) to terminate transmission lines. In one application, the Low Voltage Differential Signaling (LVDS) requires a 100 ohms termination impedance, and in addition this impedance needs to operate (i.e., remain linear) over a wide common mode range. Furthermore, when constructing terminating devices, it is desirable that this termination be realized on chip. Also, it is important that this impedance be controlled precisely to be as close to the transmission line impedance as possible. This impedance, when realized using sheet resistors exhibits a large variation due to process, temperature and power supply fluctuations. On the other hand, when active circuits are used a large variation is seen when the common mode voltage of the input signal changes. A simple way of combining the advantages of the active and passive solutions is desirable.
Various prior-art techniques have been devised to obtain controllable impedances; for example, resistors that have a value that can be set over a desired range of values. In one prior-art technique, illustrated in FIG. 1, resistors (R1 and R2) are connected in series, and paralleled with switches (SW1 and SW2). In operation, when it is desired to lower the series resistance between nodes 10 and 11, either or both of the switches SW1 and SW2 are closed, thereby effectively removing the associated resistor from the resistance path. In this manner, a total resistance of 0, R1, R2 or R1+R2 can be obtained. However, the resistance of the switches SW1 and SW2 when closed must also be taken into account if they are not small as compared to their associated resistor. In most cases, for this technique to be effective, the resistance of the switches should be less than 10 percent, and more typically less than 5 percent, of the value of the associated resistor. It is also known to use parallel MOS transistors to achieve a desired impedance, as for use in terminating a transmission line; see, for example, U.S. Pat. Nos. 5,243,229 and 5,298,800 coassigned herewith.